1. Field of Invention
The invention relates to a high-level language compiling system for a processor, particularly to a method and corresponding apparatus for compiling high-level languages into specific processor architectures.
2. Related Art
Since most multimedia and communication systems are developed in high-level program languages (such as C/C++), developers are capable of transforming the same program codes onto different platforms simply by utilizing a complier's automatic program code generating mechanism, thereby significantly reducing the time course for the product development. However, because of the increasing demand of high efficiency and low power, the digital signal processor which performs computation in the system is usually incorporated with many particular designs for various application fields, e.g., the addition of exclusive register files with particular access restriction, program flow control mechanisms with low overhead (such as hardware looping and conditional execution) and acceleration instructions for particular application fields, resulting in increasing difficulties and complexities of the compiler design, and thereby the platform transformation becomes more difficult.
Referring to FIG. 1, for example, the architecture of a digital signal processor, Packed Instructions & Clustered Architecture (PICA), is shown. The PICA digital signal processor 100 is a very long instruction set (VLIW) of a 2-way instruction slot (i.e. load/store unit 120 and arithmetic unit 122), wherein the register file (i.e. address register file 112 and accumulator 114) has a distributed architecture and employs a particular ping-pong operation mode to facilitate the data exchange between different register files (i.e. using a pair of ping and pong register files 110 to save the input and output data during data processing and transmission). In this case, a zero-overhead looping mechanism and conditional execution are provided for the program flow. However, due to various functions described above, the compiler is rather complex in respect of the design of the program codes automatic generation.
At present, the common solutions are as follows.
Referring to FIG. 2, a virtual machine 210 (e.g. a java virtual machine; JVM) is used to define a virtual architecture 220, i.e. to define a virtual processor architecture and a corresponding instruction set. Then a compiler 240 is used to compile the application program 230 into a binary bytecode 250 based on the virtual architecture 220, and then during execution, an interpreter 260 translates the bytecode 250 into a machine code 270 (i.e. a binary code) executable for the physical processor 280. Herein, when a bottom level physical processor 280 is to be altered, only the corresponding interpreter 260 is required to be re-written without the need to recompile the application program 230, and the same bytecode 250 may be reused. However, when the architecture is used to compile a high-level language application program, the generated code is hard to optimize for the physical processor architecture. Moreover, multilevel translation mechanism leads to significant efficiency reduction to the application program
Referring to FIG. 3, an abstract function interface 310 of the high-level language independent from the hardware is provided, so that in the application program 230, the desired algorithm is completed by directly linking the functions from the interface function library 320, no need for considering the true action and restrictions on computation of the processor 280. Furthermore, for different physical processors 280, only different interface function libraries 320 are required to be re-linked by the compiler 240 without rewriting the original application program 230 written in high-level languages. However, while the architecture initially uses the abstract function interface 310, the original application program 230 is required to be rewritten to comply with the action defined by its function library 320. As a result, it is rather time consuming, and in practical operation, an operating system 390 is needed for assisting the operations of the abstract function interface 310 and the physical processor 280. Moreover, the function library 320 provided under this architecture is insufficient to perform all functions provided by the physical processor 280.
In another method, the machine codes of the application programs compiled into different processor architectures are recompiled into the binary codes executable for the physical processor by using the software in a dynamic (i.e. during executing) or static manner. However, since it is hard for the architecture to acquire the relationships between the instructions in a large scale while recompiling conducted by the software, the optimization is rather limited. Meanwhile, due to the differences between the architectures of the processors, the translated program codes cannot sufficiently use the computation capability of the physical processor, thereby resulting in a low efficiency of the application programs.
Thus it is understood that base upon the actual hardware architecture technique, it is no longer difficult to develop a novel processor architecture with high efficiency, and the key factor to define the popularity in the market is whether there is a high-level language compiling system in the development environment. Moreover, for the purpose of greatly shortening the time course of the processor development and verification, it is indispensable to develop a useful compiler for the novel processor rapidly in the early development time.